Method and apparatus for computing a sliding sum of absolute differences
US8270478B2 · kind B2 · utility
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10References
14Claims
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Key dates
| Filing date | Mar 29, 2007 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Oct 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit is configured to calculate a sliding sum of absolute differences of a plurality of numbers from a plurality of members respectively selected successively from all members of a sequence of numbers. The logic circuit reduces an amount of logic that is required to perform the sum of absolute differences, and thereby saves resources and latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.