Concurrent input/output control and integrated error management in FIFO
US8271701B1 · kind B1 · utility
6Cited by
38References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2011 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | May 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.