Hierarchical error injection for complex RAIM/ECC design
US8271932B2 · kind B2 · utility
7Cited by
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21Claims
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Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.