Self-aligned metal oxide TFT with reduced number of masks
US8273600B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Aug 2, 2011 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Aug 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.