Gated-varactors
US8273616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/211
Abstract
Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.