Electronic devices and systems, and methods for making and using the same
US8273617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | May 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.