Producing a vertical transistor including reentrant profile

US8273654B1 · kind B1 · utility

Assignee

• EASTMAN KODAK COMPANY · US

Inventors

• Shelby F. Nelson · Pittsford, US
• David H. Levy · Rochester, US
• Lee W. Tutt · Webster, US

Key dates

• Filing date: Sep 29, 2011
• Grant date: Sep 25, 2012
• Expiry date: Sep 29, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6728

Abstract

Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. An electrically insulating material layer is deposited over a portion of the gate material layer stack and over a portion of the substrate. A patterned deposition inhibiting material is deposited over the electrically insulating material layer. A semiconductor material layer is deposited over the electrically insulating material layer using a selective area deposition process in which the semiconductor material layer is not deposited over the patterned deposition inhibiting material.