Coarse digital-to-analog converter architecture for voltage interpolation DAC
US8274417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/765
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.