NAND flash memory
US8274837B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2010 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Dec 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.