Unified model for process variations in integrated circuits
US8275584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | May 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318314
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.