High speed memory simulation
US8275597B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2008 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Aug 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.