Load reduction system and method for DIMM-based memory systems
US8275936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2009 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.