Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
US8275971B2 · kind B2 · utility
5Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Jul 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.