Sequencer controlled system and method for controlling timing of operations of functional units
US8275975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2008 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Feb 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.