Decoding circuit operating in response to decoded result and/or a plurality of viterbi target levels with pattern dependency
US8276053B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2009 |
| Grant date | Sep 25, 2012 |
| Priority date | — |
| Expiry date | Feb 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding circuit includes: a level adjuster with pattern dependency arranged to generate a plurality of Viterbi target levels with pattern dependency; and a Viterbi decoder arranged to perform Viterbi decoding according to the Viterbi target levels with pattern dependency. A decoding circuit includes a Viterbi decoder arranged to perform Viterbi decoding, and the Viterbi decoder includes a branch metric generator arranged to generate a plurality of branch metrics with pattern dependency according to an input of the Viterbi decoder and a plurality of Viterbi target levels with pattern dependency. In particular, the branch metric generator includes: a plurality of branch metric generation paths arranged to generate a plurality of intermediate values according to the input of the Viterbi decoder and the Viterbi target levels with pattern dependency, respectively; and a selection unit for selecting a portion of the intermediate values as the branch metrics with pattern dependency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.