Microelectronic package and method for a compression-based mid-level interconnect
US8278752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.