Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode
US8278980B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2012 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | May 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.