Continuous conduction mode power factor correction circuit with reduced sensing requirements
US8279630B2 · kind B2 · utility
5Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 14, 2008 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Mar 9, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power supply circuit includes continuous conduction mode power factor correction (PFC). The PFC may be performed by generating a carrier signal voltage at a beginning of a switching cycle of the power supply, generating a sampling voltage indicative of drain current of a drive transistor, and detecting when the carrier signal voltage has decreased to the same level as the sampling voltage at an intersection time. The ON time of the drive transistor may be set to twice the intersection time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.