Low power termination for memory modules
US8279689B2 · kind B2 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 17, 2011 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | May 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.