Device and process for data rate acquisition
US8279989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2006 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Aug 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A baud rate acquisition circuit (10) for synchronizing a sampling signal with an input signal operates in broad rate sweeping and a rate fine tuning phases. In the rate sweeping phase, a timing error detector (24) examines the sampling signal generated by a decimator (16). If the sampling signal is outside a rate acquisition range from the target rate, a rate sweeping algorithm selects a new sampling rate. In response to the sampling rate within the rate acquisition range, the timing error detector (24) examines the asymmetry thereof to generate a rate correction signal to synchronize the sampling signal with the input signal. Next in the rate fine tuning phase, a multiplexer (22) routes the sampling signal through a square root filter (18). By examining the waveform shaped signal, the time error detector (24) synchronizes the sampling signal with the input signal with high accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.