Clock generation for integrated radio frequency receivers
US8280340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2009 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Jun 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0032
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Systems of clock generation for integrated radio frequency receiver. In an integrated radio frequency receiver, a mixer is often used to down convert the incoming radio frequency signal. The down converted signal is then digitized and digital signal processing circuitry is used for efficient and flexible implementation of various functions to receive the underlying audio and/or data information. The mixer requires clock generation circuitry to provide a proper local oscillator signal for a selected channel. On the other hand, the digital signal processing circuitry requires its separate digital clock for proper operations. The clock generation system utilizes single local oscillator generation circuitry to provide the local oscillator signals required by the mixer and the digital clock signals required by the digital signal processing circuitry. In order to maintain a fixed frequency for the digital clock signal regardless channel selection, a fractional divider coupled with sigma-delta circuitry is used to derive the digital clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.