Host-daughtercard configuration with double data rate bus
US8281049B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Sep 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate bus system includes a host-network interface card configuration wherein the host is configured to recognize the network interface card to establish a double data rate bus between the host and the network interface card. The host is configured to generate a plurality of generic data frame queues. Each of the generic data frame queues is configured to receive and to transmit generic data frames via the double data rate bus. The network interface card is configured to transmit a plurality of dynamic memory access read requests to the host via the double data rate bus. The host is configured to allow each of the plurality of dynamic memory access read requests to remain pending prior to responding to any one of the plurality of dynamic memory access read requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.