Optimized correction factor for low-power min-sum low density parity check decoder (LDPC)
US8281210B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2008 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Feb 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1191
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An iterative decoder configured to implement a min-sum with correction algorithm. The iterative decoder includes N parity check nodes coupled to M equality constraint nodes. The iterative decoder further includes a first parity check node configured to send an output to a first equality constraint node. Responsive to a minimum magnitude of other M−1 inputs to the first parity check node being lower than a pre-determined threshold, the parity check node sends the output having a same magnitude as that of the minimum magnitude of the other M−1 inputs to the first parity check node. Responsive to the minimum magnitude of the other M−1 inputs to the first parity check node being greater than the pre-determined threshold, the parity check node subtracts a correction factor in the form of p·2q from the minimum magnitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.