Iterative ECC decoder with out of order completion
US8281212B1 · kind B1 · utility
3Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2008 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | May 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame using the ECC decoder that includes a faster stage and a slower stage, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed using the ECC decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.