Memory devices and encoding and/or decoding methods
US8281217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2009 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Jul 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/353
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.