Method and system for proximity-aware circuit design
US8281270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Jan 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.