Nanowire memory
US8283654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2009 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Aug 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.