Ramp-stack chip package with static bends
US8283766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Apr 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.