Array type chip resistor
US8284016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2009 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C17/02
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.