Shared memory multi video channel display apparatus and methods
US8284322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Aug 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/012
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.