Semiconductor memory device
US8284612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.