Apparatus for enhancing flash memory access
US8285917B2 · kind B2 · utility
4Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2009 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/214
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.