SSD with improved bad block management
US8285919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Mar 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.