Enhancing timeliness of cache prefetching
US8285941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2008 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.