Reducing access contention in flash-based memory systems
US8285946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2009 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Apr 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.