SMT/ECO mode based on cache miss rate
US8285950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Apr 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.