Flash memory devices with high data transmission rates and memory systems including such flash memory devices
US8286021B2 · kind B2 · utility
7Cited by
15References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Jan 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.