Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package
US8288210B2 · kind B2 · utility
4Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Mar 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.