Semiconductor memory device and manufacturing method of the same
US8288751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Jan 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/00
Abstract
A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.