Integrated devices on a common compound semiconductor III-V wafer
US8288797B2 · kind B2 · utility
1Cited by
18References
13Claims
0Family size
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Key dates
| Filing date | Dec 9, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.