Method for control of overlap times in switching power converters
US8289010B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2006 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/008
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments of a system and method to control the overlap times—and deadtime delays—in power converters may support both overlapping and non-overlapping gate control signals, which may provide improved efficiency optimization across a wider range of applications. Various embodiments may be configured to provide careful partitioning between hardware implementation and software control, in order to better accommodate microprocessor-based power converters. Software algorithms may be used to avoid restrictions such as high gate impedance and changing load effects, and protection against errant operation may be provided using an overlap watchdog circuit. Various control circuits may be operated according to one or more algorithms configured to optimize both the HS-to-LS and LS-to-HS deadtime delays for obtaining minimum possible PWM duty cycle values to achieve improved power efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.