Switching systems
US8289127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2007 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/1332
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Distributively associated with each output row of point cells or each subset of point cells in each output row is one or more of a: memory device for storing an address identifying a cell in its associated output row and a decoder device responsive to the memory device for actuating the associated enable circuit to operate the transconductance device of the identified cell; a bias device, and an output cascode device; and also disclosed as switching systems having a bias device including a current mirror with an input reference portion responsive to a reference current and a co-located output local portion for reproducing that current as the bias current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.