Output buffer circuit with enhanced slew rate
US8289302B2 · kind B2 · utility
1Cited by
5References
22Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 6, 2009 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.