Volatile memory elements with soft error upset immunity
US8289755B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Nov 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.