Page buffer, nonvolatile semiconductor memory device having the same, and program and data verification method
US8289780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.