System having a plurality of memory devices and data transfer method for the same
US8289788B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing: (i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device; (ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and (iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data. Communications between the control section and the selected memory device during the write data transmission period and the response period are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size. The control section sets a frequency of the clock signal during the response period to a lower value than that of the clock signal duri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.