Circuit, system and method for multiplexing signals with reduced jitter
US8290109B2 · kind B2 · utility
6Cited by
31References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Mar 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.