Nonvolatile semiconductor memory device with reduced size of peripheral circuit area
US8294238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Aug 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
Abstract
A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.