Low-offset charge pump, duty cycle stabilizer, and delay locked loop
US8294497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A charge pump circuit can include a first pair of transistors having connected sources and gates configured to receive a first pump signal and an inverse first pump signal and a second pair of transistors having connected drains and gates configured to receive a second pump signal and an inverse second pump signal, sources of the second pair of transistors being connected to drains of the first pair of transistors at first and second connection nodes, wherein the first and second pair of transistors are all of the same transistor type and provide an output current in response to the first and second pump signals. The charge pump circuit can also include a voltage stabilizer circuit connected to the second connection node and configured to regulate the second connection node to have a voltage within a predetermined range about a selectable voltage. Duty cycle stabilizers and control loops such as delay locked loops can include the charge pump circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.