High performance hardware linked list processors
US8295292B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Apr 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9015
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.